Fraunhofer IIS/EAS implements their BoW standard-based chiplet interface IP on Samsung’s 5 nm process technology
Dresden, Germany: Fraunhofer IIS/EAS has announced today their first implementation of the Bunch of Wires (BoW) standard-based interface IP from the Open Compute Project (OCP) on Samsung’s 5 nm technology. This work represents a first step towards supporting the rapid introduction of chiplet technology, even enabling electronic products with smaller production runs.
Today, creating a die-to-die chiplet interface is economically feasible primarily for high-volume applications. The custom implementation has largely excluded product groups with smaller and medium-sized production runs. In this sector, chiplets remain a long way off – and the benefits of this technology, like greater degrees of freedom in the selection of production technologies used for circuits, have barely been exploited.
To change this situation, Fraunhofer IIS/EAS is working to implement customizable individual solutions based on chiplets. If these solutions are to be secure and efficient, however, there will be a need for uniform standards in the future – such as for die-to-die bonding. These standards will be vital for the integration of circuits from various manufacturers and the avoidance of problems with chip assembly in small production runs.
“We are delighted to work with Fraunhofer IIS/EAS on getting their interface IP into silicon with our 5 nm process technology,” says Kevin Yee, Sr. Director of Marketing, Foundry IP and Ecosystem from Samsung Electronics. “As a leading IP partner in our SAFE™ ecosystem, and a provider of BoW-based interface IPs, which is also of interest to Samsung Foundry, we plan to work together and find ways to enable our mutual customers and the industry.”
To this end, the Fraunhofer design team used the OCP Bunch of Wires standard within the Open Domain-Specific Architecture (ODSA). “We have many years of experience in chiplet design and are delighted that we’ve now implemented a standard-based interface IP on Samsung process technology,” adds Andy Heinig, chiplet expert at Fraunhofer IIS/EAS. “As part of this work, we even managed to implement a data rate of 16 Gbit/s per lane – the highest rate specified by the BoW standard. We believe this provides an excellent basis for implementing forward-looking solutions for our customers and for a fruitful ongoing collaboration with Samsung.”
Background: Chiplets
Chip packaging solutions based on chiplets allow various functional units, including with different technologies, to be incorporated onto a substrate or into a 3D stack. For example, developers can therefore use the most suitable production technologies to concentrate functionalities requiring circuits with the latest semiconductor technologies into a few circuits instead of using them for the entire chip.
https://www.eas.iis.fraunhofer.de/en/media_press/press_releases/pr_20221110_EN.html
Wissenschaftlicher Ansprechpartner:
Andy Heinig
Head of Department Efficient Electronics
Phone +49 351 45691-250
andy.heinig@eas.iis.fraunhofer.de
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